I²S audio codec ADC/DAC interface using VHDL and the Xilinx Zynq FPGA

Learn to implement the I²S protocol in VHDL and configure the ADAU1761 ADC/DAC audio codec chip on the Xilinx Zedboard with bare-metal C programming.

What you'll get:

• Permanent access to 26 lessons
  (4 hours and 20 minutes of video)
• Downloadable code from lessons where applicable

All purchases made with the same email address share one VHDLwhiz account, created automatically on your first purchase.

This is a one-time payment. No subscription, no hidden fees. Because you get immediate access to the course, the purchase is non-refundable.

This course is also available through the separate VHDLwhiz Membership subscription.

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