VHDLwhiz Membership

The FPGA learning experience that never ends

This VHDL training program supports you in becoming successful in programmable logic design.

When you join, you get access to everything in the portal, every tutorial, and every resource.

You get a new video tutorial series and a new resource item every month. That can be a template, an example design, or something you can use to save time in your work.

Your monthly subscription fee will never increase, and you can leave whenever you want.

I know that this concept works because most of the initial members have stayed since the launch in February.

Join the community and build your confidence as an FPGA engineer! πŸ˜€

Scroll down to find out what the membership can do for you!

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Why a membership site instead of another course?

There are many brilliant coding courses, all with the same limitations:
the learning curve is steep, and there is no support after it ends.

But FPGA design isn't something you ever get done learning.

You can always become better, and that's what the membership will reflect. I want to support you on the way to reaching your goals in digital hardware design.

A learning experience that doesn't end is appropriate for a learning curve that has no ceiling.

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How the membership works

After you join, you can log in to the portal Dashboard to find all the content.

The monthly new lessons will appear in the left sidebar. I will also announce them in the News tab, and I will send you an email so that you never miss anything.

Additionally, there is a Resources library that you can use for your convenience. I will reference the resources in the tutorials to keep the videos short and on target.

We also have a Core Training series to make it easy for you in the beginning and a Stages page with assessments to track your progress.

And finally, there is a Facebook group that is only for active members. I will use the group for communicating informally with you and the other members.

Core Training

To make your onboarding experience smooth and enjoyable, I have prepared a video series that welcomes you into the membership.

In the Core Training lessons, I show you around the membership site and tell you how to set up the development environment correctly.

Finally, we create a simple VHDL module and testbench to practice the standard project setup.

Your time is valuable.

Therefore, I will introduce the tools that enable you to learn and become productive as quickly as possible.

The Core Training series brings you up to speed in no time.

Resource Library

As a member, you get access to a collection of resources that you can use to save time in your work.

Currently, the forever-growing database consists of 46 items from five subcategories.

The templates, examples, printables, and video walkthroughs for installing software make it easy for you to get started on your next project.

Most of the example designs contain a ModelSim project that you can download and run on your computer within minutes.

I will reference the resources in the lessons to keep the tutorial videos short and on the topic.

Stages of Knowledge

We will classify your skill level into five stages to help you focus and track your progress.

You can retake the questionnaires on the Stages page in the membership whenever you want.

The VHDLwhiz Membership is primarily for intermediate to advanced users. If you are an absolute beginner, I recommend starting with the Fast-Track course .

Stages of Knowledge

We will classify your skill level into five stages to help you focus and track your progress.

You can retake the questionnaires on the Stages page in the membership whenever you want.

The VHDLwhiz Membership is primarily for intermediate to advanced users. If you are an absolute beginner, I recommend starting with the Fast-Track course .

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New lessons every month

I will add a new tutorial series and one or more items to the resource library every month. You can view the content whenever you want, and you don't have to start at the beginning.

The membership is not a course; it's a learning program that supports you in achieving your goals in the long run.

Here's the current publishing schedule:

First Monday of the month
  • New tutorial series
Third Monday of the month
  • New resource(s)

You will receive an email when new content is available, and I will update the News section in the Membership portal.

Study at a pace that suits you.

Unlike a course, the membership has no beginning or end. Each tutorial series is a mini-course, and the resources are independent.

It's up to you how deep you want to immerse yourself into the world of programmable logic.

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Scroll down to the "Get instant access to these tutorial series when you join" section to see the updated list of tutorials!

What's in the portal right now?

Currently, there are eleven tutorial series available in the membership portal. That's because the membership has been going on since February 2021.

Additionally, there are 48 resource items (Templates and Scripts: 9, Example Designs: 15, Example Testbenches: 7, Printables: 5, Installation Guides: 12).

                    Get instant access to these tutorial series when you join:

Delta cycles in-depth

Understanding how delta cycles work is key to becoming proficient in VHDL. This series teaches you how signal scheduling works in the simulator.

Protected type string list

In this series, we create a dynamic string list in VHDL based on Python's list class. We use a protected type to store strings of any length and quantity in the testbench.

ZedBoard audio pass-through

This tutorial series shows how to create a system-on-chip (SoC) design using Vivado and Vitis, enabling the ADAU1761 audio codec chip on the Xilinx ZedBoard.

I2S audio interface

In this tutorial series, we create an I2S interface module in VHDL. We'll use it for sending and receiving audio samples through the ADAU1761 audio codec chip on the Xilinx ZedBoard.

I2S BFM and self-checking TB

Learn how to create a self-checking testbench (TB) that uses a bus-functional model (BFM) to verify a serial transceiver device under test (DUT).

Makefile-based workflow for Lattice

Are you ready to ditch the GUI? In this series, we convert a Lattice iCEcube2 GUI project into a script-based workflow using a Makefile.

Script-based workflow

Learn how to structure a VHDL project consisting of multiple submodules. Use scripts to derive the compile order, launch simulations in batch mode and the GUI, and run regression tests.

Constrained random verification

This tutorial teaches how to achieve functional coverage with randomized interactions by using the OSVVM VHDL framework.

Clock divider

There are several ways to implement a clock divider in FPGAs. Some are superior to others, and after watching this series, you will know which to use.

SPI master for reading ambient light sensor

Learn to create an SPI master for reading an ambient light sensor from an FPGA. We also make an SPI slave BFM for simulating the ADC chip.

Advanced BFM signaling and transaction-based TB

Build a testbench that separates bit-level logic into separate modules and uses a command interface to control executor processes.

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Monthly subscription

$25/m

Recurring monthly payment

  • New VHDL tutorial series every month
    • (Eleven available when you join)
  • One or more new resources every month
    • (48 available when you join)
  • Access to resource database with
    • Templates and scripts
    • Example designs
    • Example testbenches
    • Printables
    • Installation guides
  • Core training lessons for easy onboarding
  • Premium Facebook group for members
  • No lock-in or hidden fees
    • Cancel at any time
    • Price will not increase if you don't cancel
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