VHDL synthesis: From code to hardware

This course teaches you to recognize which digital logic your VHDL code will synthesize into. In the course, we go through 20 VHDL module examples and analyze the elaborated (RTL) and synthesized netlists in the Xilinx Vivado FPGA implementation tool.

What you'll get:

• Permanent access to 19 lessons
  (2 hours and 10 minutes of video)
• Downloadable code from lessons where applicable

All purchases made with the same email address share one VHDLwhiz account, created automatically on your first purchase.

This is a one-time payment. No subscription, no hidden fees. Because you get immediate access to the course, the purchase is non-refundable.

This course is also available through the separate VHDLwhiz Membership subscription.

Questions before buying, or need help with your purchase? Email jonas@vhdlwhiz.com