Get Started With Self-Checking Testbenches in VHDL
Join the free 5-day coding challenge!
Registration is closed
Learn how to write self-checking testbenches in VHDL. In this challenge, you will create an automatic testbench for checking a VHDL module.
Create a Self-Checking Testbench
Learn how to create an automatic VHDL testbench to check your code without the need for manual inspection.
Simulate Your VHDL Code
Run your VHDL code in the free student edition of Active-HDL. Stop the guesswork; let the simulator do the work for you!
See the Code Working
I will program my FPGA development board with the code during the live streams. You don't need to have any hardware.
The free 5-day VHDL coding challenge is your chance to learn to write self-checking testbenches like a pro. If you're learning VHDL, or if you just want to show off some skills, you should join the event.
Does it cost anything?
The coding challenge is free, but you have to join before the start date by clicking the JOIN NOW button at the bottom of this page.
When is it?
It starts on Monday, March 9, and ends on Friday, March 13. During that week, you will learn to create a proper self-checking testbench for a VHDL module. On the last day of the challenge, you will create a module by using your testbench.
What will happen during the five days?
Every day of that workweek, you will receive an exercise about VHDL coding in your inbox. I will talk about today's assignment by live streaming in a pop-up group that you have to join on Facebook. Don't worry if you can't watch live. You can always watch the recording later that day.
What do I need to do the assignments?
The Active-HDL VHDL simulator is the only software you need to have. The free student edition is available for Windows only. But if you somehow have access to it on Linux or Mac, that will work too.
Registration is Closed
Last chance to join the free 5-day VHDL coding challenge