Dot Matrix VHDL and FPGA Course

Are you learning VHDL? Do you still feel like you couldn’t manage an FPGA project on your own?

Learn what they don’t teach you at the university; how to create a real-world FPGA design from scratch to working prototype.

The Dot Matrix LED Controller FPGA Course teaches you proven VHDL methodologies that will increase your confidence as an FPGA engineer.

Trial and error is not a viable strategy when developing hardware. Learn how to structure your project and create a suite of self-checking testbenches as a professional FPGA engineer.

Get it right the first time you power on the chip.

The lectures teach you valuable skills for understanding how each code line translates into digital logic.

This course will take you from the beginner or intermediate level to being able to understand and use advanced VHDL coding constructs.

This is a hands-on course, meaning that we learn while creating something useful, not just theory and constructed examples. We are building something very real, an FPGA controller capable of rendering characters on a dot matrix LED display.

To my astonishment, it worked the first time we powered on the chip. How could it be?

It was my first serious FPGA project. Two of us were juniors, but the other half of this team of four were veterans who had been around programmable logic since the days of the EPROM PLDs. We had been developing this FPGA for almost a year, and this was the day the PCB arrived.

Now, imagine developing a software project for months and months, and having it working the first time you run the program. Not very likely. FPGA engineers don’t have the luxury of quick turnaround time, we have to hold our code to a higher standard.

Respin is not a word any project manager likes to hear.

Manufacturing PCBs is expensive and time-consuming. Not to mention the cost of a silicon respin, should your VHDL code be part of an ASIC project. Companies who engage in VHDL development all have strong demands for performance, that’s why they’re using FPGAs in the first place.

The FPGA which I was developing at the time was for an aerospace project. As you can imagine, the consequences would be dire if the FPGA malfunctioned as a result of a logic error. Still, I can sleep well at night with the knowledge of how robust our verification regime was.

You can only create what you can test.

This statement holds true in VHDL and FPGA development. That’s why most of the new features of the VHDL language are meant for testbenches, not for synthesis. The quality of your code is largely governed by how well your testbenches are performing.

For that reason, this course focuses heavily on testbenches and verification. The emphasis is on structuring your testbench suite in such a way that you never lose the overview, while at the same time enabling you to reuse code multiple places throughout the design.

Adopt methodologies that work and save time on your journey

You can get a long way by yourself, but then you reach a plateau from where it’s hard to make further progress. You end up searching the internet, bits of information here and there. Save time and learn proven VHDL design techniques right from the start.

Use the object-oriented features of VHDL in your design flow

Become more productive by using VHDL's high-level programming constructs. Take a step into the 21st century and start using dynamic data structures in your testbenches.